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document number: mc34670 rev. 3.0, 12/2006 freescale semiconductor advance information * this document contains certain information on a new product. specifications and information herein are subject to change without notice. ? freescale semiconductor, in c., 2006. all rights reserved. ieee 802.3af pd with current mode switching regulator the 34670 combines a power interface port for ieee 802.3af powered devices (pd) and a high performance current mode switching regulator. it allows a designer to build pds with a minimum of external components by means of integrating the required ieee 802.3af functions and all functions necessary to build a high efficiency dc/dc converter. on the pd side the 34670 fully supports the ieee 802.3af standard and provides complete signature and power classification functions. it controls inrush current limi ting and incorporates adjustable undervoltage lockout. the switching regulator provides excellent line and load regulation. it drives an external power mosfet with sense resistor. features ? integrated ieee 802.3af compliant interface ? signature detection and classification functionality ? integrated isolation switch ? programmable inrush current limiting control ? adjustable undervoltage lockout ? input voltage range up to 80 v ? current mode control ? adjustable oscillator ? leading edge blanking ? internal slope compensation circuitry ? input overvoltage protection ? 50% duty cycle limitation ? pb-free packaging designated by suffix code eg figure 1. 34670 simplified application diagram power over ethernet eg suffix (pb-free) 98asb42343b 20-pin soicw 34670 ordering information device temperature range (t a ) package mcz34670eg/r2 -40c to 85c 20 soicw phy phy pse hub or switch tx rx host pse power controller 48 v power supply -48v gnd cat 5 switch rj-45 processor ethernet appliance (pd) rx tx host pd power controller dc/dc -48v controller cable isolation switch 34670
analog integrated circuit device data 2 freescale semiconductor 34670 internal block diagram internal block diagram figure 2. 34670 simplifi ed internal block diagram + + + 2.5v 0.8r r internal supply high voltage regulator por osc en uv or uvlo control logic undervoltage lockout overvoltage detection 250mv current limitation gate drive temp sensor uv or uvlo r s r q 8v 5.7v 3.5v 5 a s r q 0.3v pwm comparator 4.5v 5k ? 1.4v 3 reg detect blank 0.4v 0.6v 1.2v slope comp 0.6 - 2.6v reset gate vdd ss cs comp fb vout freq vpwr rcla ilim uvlo vin r sense
analog integrated circuit device data freescale semiconductor 3 34670 pin connections pin connections figure 3. 34670 pin connections table 1. 34670 pin definitions pin number pin name formal name definition 1, 2 vpwr positive supply voltage input this is the most positive power supply i nput. the load connects between this pin and the v out pin. 3 rcla classification resistor connect a resistor between rcla and v in to select the class of the pd. 4 uvlo undervoltage lookout used to adjust the undervoltage lookout threshold voltage, connected to v in to use the default threshold voltage. 5 test1 test pins connect to v in in application mode. 6 test2 7 freq frequency adjustment adjusts the internal oscillator frequency by connecting a resistor between freq and v in . 8 ilim inrush current limit used to adjust the inrush current limit of the isolation switch, add a resistor between ilim and v in . 9 vin negative supply voltage this is the most negative power supply input. 10 vin 11, 12 vout output voltage this pin is the drain of the internal power mosfet (high current path). 13 vout output voltage this pin is the drain of the internal power mosfet (low current path). 14 reset reset output (active low) this is an active -low reset output signal. this pin is referenced to v out . 15 ss soft start input connect an external capacitor to ss. the internal current source charges the capacitor and generates a soft-start ramp. 16 comp compensation pin comp is the output of the error am plifier and is av ailable for feedback compensation. comp is pulled-up by an internal 5.0 k ? resistor to 5.0 v. 17 fb feedback input this is the inverting input of the error amplifier. in non-isolated applications it?s connected to the secondary output through a resistor divider. 18 cs current sense the current sense pin cs senses a volt age that is proportional to the current through the sense resistor. 19 gate gate driver output gate drives the gate of the external power mosfet. gate sources and sinks up to 1.0 a. 20 vdd v dd output v dd mainly supplies the gate of the exte rnal power mosfet. connect a capacitor from v dd to v out . 1 2 3 5 4 6 7 8 9 10 20 11 12 13 14 15 16 17 18 19 vpwr vpwr rcla uvlo test1 test2 freq ilim vin vin vdd gate cs fb comp ss reset vout vout vout
analog integrated circuit device data 4 freescale semiconductor 34670 electrical characteristics maximum ratings electrical characteristics maximum ratings table 2. maximum ratings all voltages are with respect to v in unless otherwise noted. exceeding these ra tings may cause a malfunction or permanent damage to the device. ratings symbol value unit electrical ratings power supply voltage v pwr -0.3 to 80 v supply current i pwr 18 ma vout pins voltage v out -0.3 to (v pwr + 0.3) v uvlo voltage v uvlo -0.3 to 10 v rcla voltage v rcla -0.3 to 5.0 v ilim voltage v ilim -0.3 to 5.0 v freq voltage v freq -0.3 to 5.0 v with respect to: v out (2) v in (3) fb, comp voltage v fb , v comp -0.3 to 5.0 -0.3 to 80 v ss voltage v ss -0.3 to 5.0 -0.3 to 80 v vdd voltage v dd -0.3 to 16 -0.3 to 80 v gate voltage v gate -0.3 to (v dd + 0.3) -0.3 to 80 v cs voltage v cs -0.3 to 5.0 -0.3 to 80 v reset voltage v reset -0.3 to 15 -0.3 to 80 esd voltage (1) human body model machine model v esd1 v esd2 2000 200 v output clamp energy e cl 12 mj notesnotes 1. esd1 testing is performed in accor dance with the human body model (c zap = 100 pf, r zap = 1500 ?). esd2 testing is performed in accordance with the machine model (c zap = 200 pf, r zap = 0 ?) . 2. measured value relative to v out 3. measured value relative to v in
analog integrated circuit device data freescale semiconductor 5 34670 electrical characteristics maximum ratings thermal ratings operating temperature ambient (4) junction (8) , (9) t a t j -40 to 85 120 c storage temperature t stg -65 to 150 c power dissipation (t a = 25 c) (7) p d 800 mw thermal resistance junction to ambient 20ld soic w/b package (9) r ja r jb 103 47 c/w peak package reflow temperature during reflow (5) , (6) t pprt note 6 c thermal shutdown temperature t shut 180 c thermal shutdown recovery temperature t hyst 150 c notesnotes 4. the limiting factor is junction temperatur e; taking into account the power dissipat ion, thermal resistance, and heat sinking. 5. pin soldering temperature limit is for 10 seconds maximum dur ation. not designed for immersion soldering. exceeding these lim its may cause malfunction or permanent damage to the device. 6. freescale?s package reflow capability meets pb-free requirements for jedec standard j-std-020c. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.freescale.com, search by part number [e.g. remove pref ixes/suffixes and enter the core id to view all orderable parts . (i.e. mc33xxxd enter 33xxx), and review parametrics. 7. maximum power dissipation at indicated ambient temperature in free air with no heatsink used. 8. for t a = 85c and p d = 700 mw and r jb = 47c/w. 9. measured with 4 layers 2s2p jedec std. pcb. table 2. maximum ratings (continued) all voltages are with respect to v in unless otherwise noted. exceeding these ra tings may cause a malfunction or permanent damage to the device. ratings symbol value unit
analog integrated circuit device data 6 freescale semiconductor 34670 electrical characteristics static electrical characteristics static electrical characteristics table 3. static electric al characteristics characteristics noted under conditions 30 v v pwr 60 v, - 40 c t a 85 c, v in = 0 v unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit signature detection input offset current (1.4 v v port 9.5 v) i offset ? ? 10 a differential input resistance (1.4 v v port 9.5 v) r diff 600 ? ? k ? classification classification current (13.5 v v port 20 v) class 0: r class = 4.42 k ? class 1: r class = 475 ? class 2: r class = 261 ? class 3: r class = 169 ? class 4: r class = 113 ? i class 0 9.0 17 26 36 ? ? ? ? ? 4.0 12 20 30 44 ma classification current limit i class(lim) ? ? 50 ma rcla reference voltage (13.5 v v port 20 v) v rcla 4.0 4.5 5.0 v inrush current limitation (37 v v port 60 v) (rlim) input inrush current, ilim connected to v in i inrush ? ? 350 ma input inrush current, ilim connected via resistor r ilim to v in r ilim = 12.1 k ? r ilim = 42.2 k ? r ilim = 191 k ? i inrush 130 70 30 180 110 65 250 165 100 normal operatio n (vpwr, uvlo) supply voltage v pwr ? ? 60 v supply current (10) i pwr ? 4.5 7.3 ma default turn-on voltage (uvlo = v in ) v uvlo(on) ? ? 40 v default turn-off voltage (uvlo = v in ) v uvlo(off) 30 ? ? v uvlo hysteresis when set internally v hyst(int) 6.0 ? ? v external uvlo programming range v uvlo(pr) 25 ? 50 v uvlo reference voltage v uvlo(ref) 1.96 2.0 2.04 v uvlo hysteresis when set externally v hyst(ext) ? 15 ? % uvlo bias current i uvlo(b) ? ? 1.0 a isolation switch (ilim) on-resistance (v port = 48 v, i port = 350 ma) (11) r ds(on) ? ? 500 m ? isolation switch current limi t in normal operation mode i lim 380 ? 700 ma notes 10. gate pin open, pwm controller running. 11. measured across v in and v out .
analog integrated circuit device data freescale semiconductor 7 34670 electrical characteristics static electrical characteristics pwm comparator (comp) comp control voltage range v comp 1.3 ? 4.0 v comp input bias current i comp(b) ? ? 1.8 ma high voltage regulator regulator output voltage vdd reg 8.0 9.0 10 v regulator turn-off voltage (12) v reg(off) vdd reg +0.5 ? v regulator current limitation (13) i reglim 7.0 ? 15 ma regulator continuous current i regdc ? ? 5.0 ma gate driver (uvlo) gate driver uvlo, rising v gate(r) vdd-0.5 ? ? v gate driver uvlo, falling v gate(f) ? ? 6.5 v current limit (cs) cs threshold voltage v cs 320 400 480 mv cs bias current i cs(b) ? ? 30 a error amplifier reference voltage v ref 1.164 1.2 1.236 v overvoltage shutdown ovlo threshold, rising v ov(r) 66 ? 72 v ovlo threshold, falling v ov(f) 63 ? 69 v ovlo hysteresis v ov(hys) ? 3.0 ? v soft-start (ss) ss output voltage v ss ? 2.0 ? v ss source current i ss(out) 3.25 5.0 6.75 a ss sink current i ss(in) ? 2.0 2.25 ma shutdown threshold voltages v ss(r) v ss(f) 0.48 0.24 0.6 0.3 0.72 0.40 v thermal shutdown thermal shutdown temperature t shutdown 150 165 180 c thermal hysteresis t hys ? 30 ? c notes 12. an external voltage has to be applied. 13. thermal limitations of the devic e might derate usable current range. table 3. static electrical characteristics(continued) characteristics noted under conditions 30 v v pwr 60 v, - 40 c t a 85 c, v in = 0 v unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 8 freescale semiconductor 34670 electrical characteristics dynamic electrical characteristics dynamic electrical characteristics table 4. dynamic electri cal characteristics characteristics noted under conditions 30 v v pwr 60 v, - 40 c t a 85 c, v in = 0 v unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit normal operation turn-on filter time t filt(on) ? 200 ? s turn-off filter time t filt(off) ? 200 ? s pwm comparator slope compensation ramp as a function of switching frequency f pwm = 100 khz f pwm = 250 khz f pwm = 400 khz m 100 m 250 m 400 ? ? ? 10 25 40 ? ? ? mv/ s duty cycle limit (14) d max ? ? 48 % gate driver rise time (10% - 90%), c load = 2.0 nf, vdd reg = 9.0 v t r ? ? 50 ns fall time (90% - 10%), c load = 2.0 nf, vdd reg = 9.0 v t f ? ? 30 ns current limit blanking time (14) t blank 40 50 60 ns pwm oscillator default clock frequency (freq connected to v in ) f pwm 175 225 325 khz oscillator frequency adjusting resistor range r freq 121 ? 499 k ? oscillator frequency range, r freq = 121 k ? f range 320 ? 480 khz oscillator frequency range, r freq = 499 k ? f range 80 ? 120 khz error amplifier gain bandwidth (14) gbw 1.0 ? ? mhz dc open loop gain a vol ? 80 ? db reset output reset output low voltage (i reset, sink = 20 ma) v reset,low ? ? 0.8 v reset output filter time t reset ? 20 ? s notes 14. guaranteed by design. not production tested.
analog integrated circuit device data freescale semiconductor 9 34670 electrical characteristics typical switching waveforms typical switching waveforms figure 4. drain voltage of switching mosfet figure 5. secondary and output voltage figure 6. secondary voltage before diode figure 7. gate voltage and voltage at cs pin w/o snubber w/ snubber w/ snubber w/o snubber
analog integrated circuit device data 10 freescale semiconductor 34670 electrical characteristics electrical performance curves electrical per formance curves figure 8. efficiency plot mc34670 efficiency plot: v o = 5v, w/ bias windin g , coilcraft da2362-al 50.00 55.00 60.00 65.00 70.00 75.00 80.00 85.00 90.00 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 i o [a] % 57v 48v 36v mc34670 efficiency plot: v o = 5v, w/o bias windin g , coilcraft da2142-al 50.00 55.00 60.00 65.00 70.00 75.00 80.00 85.00 90.00 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 i o [a] % 57v 48v 36v
analog integrated circuit device data freescale semiconductor 11 34670 functional description introduction functional description introduction the 34670 combines a power interface port for ieee 802.3af powered devices (pd) and a high performance current mode switching regulator. it allows a designer to build pds with a minimum of external components by means of integrating the required ieee 802.3af functions and all functions necessary to build a high efficiency dc/dc converter. thus 34670 gives the system designer a device that drastically reduce s cost and board space. on the pd side th e 34670 fully supports the ieee802.3af standard and provides comple te signature detection and power classification functions. it controls inrush current limiting and incorporates an adjustable undervoltage lockout. the 34670 includes thermal protection circuitry to protect the device in case of high power dissipation. the 34670 also offers an input overvoltage detection to protect the external switching mosfet by disabling the gate driver in case of input line overvoltage. the switching regulator provides excellent line and load regulation. it drives an external power mosfet with sense resistor. the switching frequency is adjustable between 100 khz and 400 khz. the output voltage feedback information can be accomplished by an optocoupler, if isolation is required. an internal logic control block manages the sequencing of signature detection, classification and proper turn on and turn off of the dc/dc converter. functional pin description positive supply voltage input (vpwr) this is the most positive power supply input. the load connects between this pin and the v out pin. classification r esistor (rcla) connect a resistor between rcla and v in to select the class of the pd. undervoltage lookout (uvlo) used to adjust the undervoltage lookout threshold voltage, connected to v in to use the default threshold voltage. test pins (test1, test2) connect to v in in application mode. frequency adjustment (freq) adjusts the internal oscillator frequency by connecting a resistor between freq and v in . inrush current limit ( ilim) used to adjust the inrush current limit of the isolation switch, add a resistor between ilim and v in . negative supply voltage (vin) this is the most negative power supply input. output voltage (vout) this pin is the drain of the internal power mosfet (high current path and low current path). reset output (reset) this is an active -low reset output signal. this pin is referenced to v out . soft start input (ss) connect an external capacitor to ss. the internal current source charges the capacitor and generates a soft-start ramp. compensation pin (comp) comp is the output of the e rror amplifier and is available for feedback compensation. comp is pulled-up by an internal 5.0 k ? resistor to 5.0 v. feedback input (fb) this is the inverting input of the error amplifier. in non- isolated applications it?s connec ted to the secondary output through a resistor divider. current sense (cs) the current sense pin cs s enses a voltage that is proportional to the current through the sense resistor. gate driver output (gate) gate drives the gate of the external power mosfet. gate sources and sinks up to 1.0 a. vdd output (vdd) v dd mainly supplies the gate of the external power mosfet. connect a capacitor from v dd to v out .
analog integrated circuit device data 12 freescale semiconductor 34670 functional device operation operational modes functional device operation operational modes power devices (pd) interface the pd interface of the 34670 has been designed to comply with the requirements of the ieee standard 802.3af. the device operates in thr ee different modes, depending on the input voltage. pd operating modes the ieee 802.3af st andard defines thre e operating modes in general. these modes are summarized in table 5 . signature resistor detection a pd shall present a valid detection signature at the pd input connector to get properly detected as a power over lan enabled pin. valid and non-valid detection signature regions are separated by guard bands. see figure 9 for valid and non-valid signature regions. figure 9. signature resistance guard bands the effective resistance across the input pins is calculated by two subsequent voltage-current measurements made during the detection process by the pse. valid pd detection signature characteristics during signature detection phase the power sourcing equipment (pse) applies a voltage in the range 2.7 v - 10.1 v on the pi connector and looks for the 25 k ? signature resistor. since the pd circuitry includes bridge rectifiers, the pd has to compensate for the voltage drop across the diodes and the diodes serial resistance. the effective signature resistance dr is obtained by the v-i-slope measurement of the pse ( figure 10 ). it can be seen in figure 11 , that a signature resistor of 25 k ? as defined in ieee 802.3af and two diodes in series would lead to an effective resistance out of the valid region specified in figure 9 . at low voltages the effective resistance is above the maximum allowed value of 26.25 k ? , as illustrated in figure 11 . therefore one has to adjust the signature resistor rsig (r 1 and r 2 , see uvlo adjustment on page 13 ) to a value below 25 k ? to stay within the valid region. figure 11. dr at low input voltages table 5. pd operating modes operating mode voltage at pd input connector signature resistor detection 2.7 v - 10.1 v classification 14.5 v - 20.5 v normal operation mode 37 v - 57 v signature [k ? ] non-valid region 12 23.75 26.25 45 non-valid region valid region i v i 1 i 2 v 1 v 2 r d v 2 v 1 ? i 2 i 1 ? -------------------- - = figure 10. dr measurement
analog integrated circuit device data freescale semiconductor 13 34670 functional device operation operational modes classification a pd may optionally be classified by the pse. the intent of classification is to provide a method for more efficient power allocation through the pse. the pd classification allows the pse to identify fo ur different (p ower) classes depending on the required power that the pd will draw during normal operation. the classes and the corresponding maximum power drawn by the pd is shown in table 6 . table 6. pd classes pd classes during classification probin g by the pse, the pd applies the appropriate load current on to the line. the pse measures the load current and can determine the classification as described in table 7 . . classification signature load current the implementation for the classification circuitry is shown in figure 12 . figure 12. classification circuitry a constant voltage is applied at pin rcla and depending on the resistor r class , a current from +v port to -v port is flowing with the following relation: i class is the classification curr ent that is measured by the pse. the values for the r class resistor corresponding to the appropriate class are listed in table 8 . uvlo adjustment the 34670 has default uvlo settings that corresponds to the ieee 802.3af sta ndard. nevertheless th e user can adjust the uvlo by an external resistor divider as sketched in figure 13 . since the uvlo resistor divider replaces the class usage maximum power [w] 0 default 0.44 - 12.95 1 optional 0.44 - 3.84 2 optional 3.84 - 6.49 3 optional 6.49 - 12.95 4 reserved ? table 7. pd class vs. classification current class classification current [ma] condition min max 0 0 4 14.5 - 20.5 volts measured at pd input connector 1 9 12 2 17 20 3 26 30 4 36 44 table 8. pd class vs. class ification resistor r class class classification current [ma] r class [ ? ] 0 2.0 4.42k 1 10.5 475 2 18.5 261 3 28 169 4 40 113 +v port -v port r class rcla vpwr vin 34670 v ref - + i class en i class v rcla r class -------------------- - =
analog integrated circuit device data 14 freescale semiconductor 34670 functional device operation operational modes signature resistor, the total resistance of r 1 +r 2 must equal 25 k ? . figure 13. uvlo adjustment by external resistor divider to use the default settings for uvlo, the pin uvlo must be connected to vin. in this ca se, a valid signature resistor has to be placed between -v port and +v port . this configuration can be seen in figure 14 . figure 14. default uvlo settings to calculate the values for r 1 and r 2 the following equations should be used: where v uvlo(on) is the desired turn-on voltage threshold and v uvlo(ref) the uvlo reference voltage. the typical turn-off voltage v uvlo(off) is 85% of the turn on voltage v uvlo(on) . inrush current limitation the 34670 has been designed to interface also with legacy poe-pses which do not meet the inrush current requirement of the ieee 802.3af specification. by setting the initial inrush current limit to a low level, a pd using the 34670 minimizes the current drawn from the pse during start-up. the maximum inrush current level can be set by connecting a resistor from ilim to v in as illustrated in figure 15 . figure 15. inrush current limita tion by external resistor r ilim the following table shows the selectable current limits and the corresponding resistor value that has to be connected between pins ilim and vin: after powering up, the 34670 switches to the high level current limit, thereby allowing the pd to consume up to 12.95 w if a 802.3af pse is present. pulse with modulator controller current-mode control operation the 34670 offers current-mode control operation with leading-edge blanking. the current -limit comparator monitors the cs pin at all times and pr ovides cycle-by-cycle current limit. the cs signal contains a leading-edge spike that is the result of the mosfet gate charge current, capacitive and diode reverse recovery current of the power circuit. the leading-edge blanking of the cs signal prevents the pwm comparator from premature termination of the on cycle. the 34670 limits the duty cycle to 50%. this is advantageous for applications which are not allowed to exceed an on-time of 50 % of the switching period t s . beside the duty-cycle limit, slope co mpensation is provided to stabilize the inner current loop and avoid oscillations for r 2 r 1 -v port +v port rcla vpwr uvlo ilim vin r sig 25k ? -v port +v port rcla vpwr uvlo ilim vin r 1 r 2 +r sig = r 2 v uvlo ref () v uvlo on () --------------------------------- - r sig ? = table 9. inrush current limit vs. r ilim inrush current limit [ma] r ilim value [k ? ] 180 12.1 110 42.2 65 191 r 1 r sig r 2 ? = v uvlo off () v uvlo on () 0.85 ? = r sig 25k ? -v port +v port rcla vpwr uvlo ilim vin r ilim r class
analog integrated circuit device data freescale semiconductor 15 34670 functional device operation operational modes converters running in contin uos conduction mode (ccm). the value of the slope compensation depends on the switching frequency. see table 10 . isolated optocoupler feedback isolated voltage feedback can be accomplished by using an optocoupler and a shunt regulator (see figure 19 ). the output voltage accuracy is a function of the accuracy of the shunt regulator and feedback resistor divider tolerance, therefore the feedback resistors should have an appropriate accuracy. since the error amplifier function is implemented on the secondary side by the optocoupler and a 3-pin adjustable shunt regulator, the internal er ror amplifier of the 34670 is not used. the fb pin is connected to v out , thus disabling the internal open-drain error amplifier. the bias voltage for the optocoupler is accomplished through the internal 5.0 k ? pull-up resistor between comp and an internal 5.0 v reference. when a tl431 or tlv431 shunt regulator is used for output voltage regulation, the out put voltage is set by the ratio of resistors r 1 and r 2 , see figure 16 for details. the output voltage is given by the following equation: where v ref = 1.24 v for the tlv431 (v ref = 2.5 v for the tl431). figure 16. isolated optocoupler feedback isolated primary control feedback another option to accomplish isolated feedback is the use of a tertiary winding (see figure 21 ). the advantage of this solution without optocoupler and shunt regulator is clearly the cost effectiveness. nevertheles s the line and load regulation is worse than with optocoupler feedback. when isolated primary feedba ck is used, the loop compensation components are connected between pins comp and fb. internal regulators the internal high voltage regulator of the 34670 regulates from the input voltage acro ss vpwr and vin down to the v dd voltage. during start-up t he high voltage regulator provides the necessary voltage fo r the internal gate driver to commence switching. if the external mosfet gate drive pulls less than 3.0 ma under all circumstances, an auxiliary transformer winding that usually provides the bias voltage for the chip and the gate dr iver is not required. in cases where the external mosfet gate drive pulls more than 5.0 ma, an auxiliary winding is needed to reduce the power dissipation in the internal high voltage ldo. see figure 18 for an application drawing. it is recommended to add a 0.1 f ceramic capacitor in parallel with the existing load capacitor. this reduces noise at the v dd pin caused by the auxiliary winding. the high voltage regulator is disabled when the v dd pin is forced by an external voltage above the v dd regulation point. table 10. slope compensation values switching frequency [khz] slope compensation [mv/ s] 100 10 250 25 400 50 v o v ref 1 r 1 r 2 ------- + ?? ?? ?? ? = t1 n p n s r v r 1 tlv431 r 2
analog integrated circuit device data 16 freescale semiconductor 34670 functional device operation operational modes this reduces power dissipation in the device and improves overall efficiency. figure 17. v dd and mosfet driver output behavior a load capacitor connected to v dd ensures a proper filtering of the v dd voltage. the minimum capacitance value for this load capacitor should be at least 10 f. an electrolytic type capacitor is sufficient. please refer to application note a/n3279 for further information about the size of the capacitor. if v dd falls below the uvlo threshold, the voltage regulator is disabled and the mosfet driver output (gate) is held low. pwm controller uvlo, soft-start, and shutdown function the soft-start function provi ded by the 34670 allows the output voltage to ramp up in a controlled way, thus eliminating output voltage overshoot. while the pwm controller is in undervoltage lockout, the capacitor c ss connected to the ss pin is fully discharged. after coming out of undervoltage lockout, an internal current source starts charging the capacitor c ss to initiate soft-start. when v ss has reached 0.6 v, the gate driver is enabled and pwm operation begins. the duty cycle during soft-start is primarily controlled by the in ternal sawtooth voltage and the voltage at the ss pin. if the voltage at the ss pin is above 2.6 v, the regular pwm control through pins cs, comp, and fb takes over and soft-start is finished. the following equation calculates the total soft-start time: overvoltage shutdown the 34670 includes an overvoltage protection (ovp) feature that turns off the ex ternal mosfet when the input voltage exceeds the overvoltage threshold. when the overvoltage protection is triggered (v pwr > v ov(r) ), the gate driver is immediately disabled. at the same time, the slow discharge of c ss is initiated. while the soft-start capacitor is discharging, the gate driver remains disabled. once v ss = 0.3 v and the overvoltage (v pwr < v ov(f) ) condition disappears, operation resumes through a regular soft-start. current-sense comparator the current-sense (cs) com parators and its associated circuitry limits the peak current through the mosfet. current is sensed at cs pin as a voltage across the sense resistor r cs between the source of the mosfet and v out . the cs input has two voltage trip levels, a 600mv high limit and a 400 mv low limit. when the voltage on cs produced by a current through the current sense resistor exceeds the high limit threshol d, the current on-cycle is immediately terminated and th e gate output is pulled low. if the low limit threshold is exceeded for longer than 50 ns (typical blanking ti me), the current on-cycle is also terminated. the blanking time ens ures a false termination of the switching cycle caused by the leading-edge spike on the sense waveform. the current-sense resistor r cs is selected according to the following equation: where i lim(primary) is the maximum peak primary-side current. in case of an overcurrent in the external mosfet the current switching cycle is terminated and gate is pulled low. the soft-start capacitor c ss is discharged and after removal of the faulty condition the pwm is re-started through a regular soft start. pwm oscillator a default 250 khz oscillator sets the switching frequency of the pwm controller. the fre quency of the oscillator can be adjusted between 100 khz and 400 khz by an optional external resistor r freq connected from the freq pin of the integrated circuit to v in . the appropriate switching frequency f pwm can be calculated as shown below: where f pwm is the pwm switching frequency and r freq is the frequency adjusting resistor. to use the default frequency of 250 khz the freq pin can be connected to v in or can be left open. reset output the reset pin is an open drain output. the reset control circuit supervises the fb voltage and recognizes if the output hvreg enable gate enable 10 2 4 6 8 v gate(r) v reg(off) 12 v gate(f) v dd t t ss ms [] 0.4 c ss nf [] ? = r cs 400mv i lim primary () ---------------------------------------- = f pwm khz [] 47920 r freq k ? [] ----------------------------------- -4 + =
analog integrated circuit device data freescale semiconductor 17 34670 functional device operation operational modes voltage is out of regulat ion. in this case the reset pin is pulled low. the reset output can only be used in non-isolated applications. there is a 20 s delay filter preventing erroneous reset output pulses. during soft-start, reset is held low. reset is released when the pwm controller is in regulation. n-channel mosfet gate driver gate drives an n-channel mosfet. gate sources and sinks large transient currents up to 1.0 a to charge and discharge the mosfet gate. the gate output is supplied by the internal generated v dd voltage, which is internally set to approximately 9.0 v. for power-over-ether net applications, the used mosfet must be able to withstand a dc level of ~60 v plus the reflected voltage at the primary side of the transformer. this requires a mosfet rated at 150 v or 200 v.
analog integrated circuit device data 18 freescale semiconductor 34670 typical applications typical applications please refer to application note an3279 for further information of pd design and layout recommendations. figure 18. isolated flyback converter with bias winding figure 19. isolated flyback converter without bias winding 3 6 1 2 4 5 8 7 rx tx c port r class m1 r cs t1 v out = 5v@2a r 2 r 1 n p n s n aux -v port +v port c ss c in r v c dd 0.1 f ss vpwr rcla uvlo ilim vin vout fb cs gate vdd freq reset comp 34670 3 6 1 2 4 5 8 7 rx tx c port r class m1 r cs t1 v out = 5v@2a r 2 r 1 c dd d 1 n p n s r v -v port +v port c ss c in rx + rx - tx + tx - spare + spare - v port ss vpwr rcla uvlo ilim vin vout fb cs gate vdd freq reset comp 34670
analog integrated circuit device data freescale semiconductor 19 34670 typical applications figure 20. isolated forward converter figure 21. isolated flyback with primary control 3 6 1 2 4 5 8 7 rx tx c port r class m1 r cs t1 r 2 r 1 c dd n p n s r v r v1 -v port +v port r v2 c ss c in n r ss vpwr rcla uvlo ilim vin vout fb cs gate vdd freq reset comp 34670 3 6 1 2 4 5 8 7 rx tx c port r class m1 r cs t1 v out = 5v@2a r 2 r 1 c dd n p n s n aux -v port +v port c ss c in c 2 c 1 r 2 c aux ss vpwr rcla uvlo ilim vin vout fb cs gate vdd freq reset comp 34670
analog integrated circuit device data 20 freescale semiconductor 34670 typical applications figure 22. non-isolated flyback converter 3 6 1 2 4 5 8 7 rx tx c port r class m1 r cs t1 c o v out = 5v@2a r 4 r 3 c dd d 1 n p n s r 1 -v port +v port r b c ss c in c 2 c 1 r 2 ss vpwr rcla uvlo ilim vin vout fb cs gate vdd freq reset comp 34670
analog integrated circuit device data freescale semiconductor 21 34670 reference documents reference documents table 11. reference documents title literature order number publication date ieee std 802.3af ? -2003 ieee std 802.3af ? -2003 18 june 2003 mc34670 usage and configuration an3279
analog integrated circuit device data 22 freescale semiconductor 34670 packaging package dimensions packaging package dimensions for the most current package revision, visit www.freescale.com and perform a keyword search using the ?98a? listed below. eg suffix (pb-free) 20-pin plastic package 98asb42343b issue j
analog integrated circuit device data freescale semiconductor 23 34670 revision history revision history revision date description of changes 1.0 8/2006 ? initial release 2.0 9/2006 ? change to uvlo hysteresis when set internally on page 6 , regulator current limitation (13) on page 7 , ovlo threshold, rising on page 7 , ovlo threshold, falling on page 7 , shutdown threshold voltages on page 7 , and default clock frequency (freq connected to vin) on page 8 ? changed data sheet category to ?advanced information*? 3.0 12/2006 ? typ and max change to rcla reference voltage (13.5 v v port 20 v) on page 6 ? deleted oscillator frequency adjusting resistor range in static electrical characteristics ? split oscillator frequent range into two parameters, oscillator frequency range, r freq = 121 k ? on page 8 and oscillator frequency range, r freq = 499 k ? on page 8 ? added note to duty cycle limit (14) on page 8 , blanking time (14) on page 8 , and gain bandwidth (14) on page 8 ? changed nomenclature for peak package reflow temperature during reflow (5) , (6) on page 5 ? changed name and value for thermal shutdown recovery temperature on page 5
mc34670 rev. 3.0 12/2006 information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability ar ising out of the application or use of any product or circuit, and specifically discl aims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale se miconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the fa ilure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemni fy and hold freescale semiconductor and its officers, employees, subsidiaries, affili ates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc., 2006. all rights reserved. how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com

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